October 31 - November 1 - Co-Located Events
October 28-30 - Conference
Lyon Convention Centre - Lyon, France
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Tuesday, October 29 • 14:25 - 15:00
RISC-V Boot Process: One Step at a Time - Atish Kumar Patra, Western Digital

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A well-supported and standard boot flow is very important for the RISC-V software ecosystem before RISC-V can be a truly competitive alternative to existing mainstream ISAs. However, RISC-V also needs its own trusted firmware to handle RISC-V specific features such as Supervisor Binary Interface (SBI) that allows the operating systems to interact with the supervisor execution environment (SEE). In this talk, Atish will discuss the status of a separate but modular open source SBI implementation (aka OpenSBI) that provides RISC-V specific run time services and how it helps in porting other common boot loaders such as U-Boot, coreboot and EDK2 to RISC-V. He will also discuss how the RISC-V boot process compares to other ISAs and where the community is heading.



Principal R&D Engineer, Western Digital
Atish is a Linux kernel engineer working at Western Digital research. He has contributed to virtualization, early boot code and drivers in Linux kernel and open source firmware for RISC-V.

Tuesday October 29, 2019 14:25 - 15:00
Salon Pasteur
  • Session Slides Included Yes